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? semiconductor components industries, llc, 2010 may, 2010 ? rev. 6 1 publication order number: ncp348/d ncp348, ncp348ae positive overvoltage protection controller with internal low r on nmos fet and status flag the ncp348 is able to disconnect the systems from its output pin in case wrong input operating conditions are detected. the system is positive overvoltage protected up to +28 v. due to this device using internal nmos, no external device is necessary, reducing the system cost and the pcb area of the application board. the ncp348 is able to instantaneously disconnect the output from the input, due to integrated low r on power nmos (65 m ), if the input voltage exceeds the overvoltage threshold (ovlo) or undervoltage threshold (uvlo). at powerup ( en pin = low level), the v out turns on 50 ms after the v in exceeds the undervoltage threshold. the ncp348 provides a negative going flag ( flag ) output, which alerts the system that a fault has occurred. in addition, the device has esd ? protected input (15 kv air) when bypassed with a 1.0 f or larger capacitor. features ? overvoltage protection up to 28 v ? on ? chip low r ds(on) nmos transistor: 65 m ? internal charge pump ? overvoltage lockout (ovlo) ? undervoltage lockout (uvlo) ? internal 50 ms startup delay ? alert flag output ? shutdown en input ? compliance to iec61000 ? 4 ? 2 (level 4) 8.0 kv (contact) 15 kv (air) ? esd ratings: machine model = b human body model = 3 ? 10 lead wdfn 2.5x2 mm package ? this is a pb ? free device applications ? cell phones ? camera phones ? digital still cameras ? personal digital applications ? mp3 players wdfn10 mt suffix case 516aa pin connections http://onsemi.com marking diagram bai = ncp348 baj = ncp348ae m = date code = pb ? free package (top view) in out 1 flag nc gnd nc in en q in out 2 3 4 5 10 9 8 7 6 pad1 gnd pad2 in baxm ordering information see detailed ordering and shipping information in the package dimensions section on page 12 of this data sheet.
ncp348, ncp348ae http://onsemi.com 2 figure 1. t ypical application circuit bat 10 vsns 9 v2p8 7 en 6 1 isel 8 timer 4 gnd 5 3 2 ncp1835b in 1 out 6 gnd 2 10 3 in 4 in 5 out 7 nc 8 nc 9 ncp348 0 d3 7011x/sm 4.7 f 15 pf 100 nf 1 f 270 k 1 m v2p8 enable / microprocessor wall adapter ? ac/dc lithium ba ttery 0 v bat cflg fault v cc v bat v bat v bat enable / microprocessor en flag figure 2. functional block diagram input output v ref v ref disable ovlo uvlo uvlo ovlo v reg v reg esd protection core negative protection power on esd protection gate driver 60 ma flag 10 v en en block esd protection 200 khz delay generator oscillator ldo v ref charge pump output impedance = 200 k
ncp348, ncp348ae http://onsemi.com 3 pin function description pin no. symbol function description 1 4 5 in power input voltage pin. this pin is connected to the power supply. the device system core is supplied by this input. a 1 f low esr ceramic capacitor, or larger, must be connected between this pin and gnd. the three in pins must be hardwired to common supply. 2 gnd power ground 3 flag output fault indication pin. this pin allows an external system to detect a fault on in pin. the flag pin goes low when input voltage exceeds ovlo threshold or drop below uvlo threshold. since the flag pin is open drain functionality, an external pull up resistor to v cc must be added. 6 7 out output output voltage pin. this pin follows in pin when ?no fault? is detected. the output is disconnected from the v in power supply when the input voltage is under the uvlo threshold or above ovlo threshold. the two out pins must be hardwired to common supply. 8 nc open no connect 9 nc open no connect 10 en input enable pin. the device enters in shutdown mode when this pin is tied to a high level. in this case the output is disconnected from the input. to allow normal functionality, the en pin shall be connected to gnd to a pull down or to a i/o pin. this pin does not have an impact on the fault detection. pad1 pad1, under the device. see pcb recommendations page 10. can be shorted to gnd. pad2 the pad2 is electrically connected to the internal nmos drain and connected to pins 4 and 5. see pcb recommendations page 10. maximum ratings rating symbol value unit minimum v oltage (in to gnd) vmin in ? 0.3 v minimum v oltage (all others to gnd) vmin ? 0.3 v maximum voltage ( in to gnd) vmax in 30 v maximum voltage (all others to gnd) vmax 7.0 v maximum current (uvlo ncp348, ncp348ae http://onsemi.com 4 electrical characteristics (min/max limits values ( ? 40 c < t a < +85 c) and v in = +5.0 v. typical values are t a = +25 c, unless otherwise noted.) characteristic symbol conditions min typ max unit input voltage range v in ? 1.2 ? 28 v undervoltage lockout threshold (note 4) uvlo ? 3.0 3.25 3.5 v undervoltage lockout hysteresis uvlo hyst ? 20 50 100 mv overvoltage lockout threshold (note 4) ncp348mtt ncp348aemtt ovlo v in rises up ovlo threshold 6.0 5.7 6.4 6.02 6.8 6.4 v overvoltage lockout hysteresis ncp348mtt ncp348aemtt ovlo hyst ? 50 30 100 60 150 90 mv v in versus v out resistance r ds(on) v in = 5.0 v, en = gnd, load connected to v out ? 65 120 m supply quiescent current idd no load. en = 5.0 v ? 90 150 a no load. en = gnd ? 170 250 a uvlo supply current idd uvlo v in = 2.9 v ? 70 100 a flag output low voltage vol flag 1.2 v < v in < uvlo sink 50 a on/flag pin ? 20 400 mv v in > ovlo sink 1.0 ma on flag pin ? ? 400 mv flag leakage current flag leak flag level = 5.0 v ? 1.0 ? na en voltage high vih ? 1.2 ? ? v en voltage low vol ? ? ? 0.4 v en leakage current en leak en = 5.0 v or gnd ? 1.0 ? na timings startup delay ton from v in : (0 to (ovlo ? 300 mv) < v in < ovlo) to v out = 0.3 v rise time<4 s (see figures 3 & 7) 30 55 70 ms flag going up delay tstart from v out = 0.3 v to flag = 1.2 v (see figures 3 & 9) 30 50 70 ms output turn off time toff from v in > ovlo to v out < = 0.3 v (see figures 4 & 8) v in increasing from 5.0 v to 8.0 v at 3.0 v/ s, rload connected on v out ? 1.5 5.0 s alert delay tstop from v in > ovlo to flag < = 0.4 v (see figures 4 & 10) v in increasing from 5.0 v to 8.0 v at 3.0 v/ s, rload connected on v out ? 1.0 ? s disable time tdis from en > = 1.2 v to v out < 0.3 v rload = 5.0 (see figures 5 & 12) ? 1.0 5.0 s note: electrical parameters are guaranteed by correlation across the full range of temperature. 4. additional uvlo and ovlo thresholds ranging from uvlo and from ovlo can be manufactured. contact your on semiconductor representative for availability.
ncp348, ncp348ae http://onsemi.com 5 timing diagrams flag v out v in uvlo t on 0.3 v t start 1.2 v ncp348, ncp348ae http://onsemi.com 6 typical operating characteristics figure 7. startup v in = ch1, v out = ch3 figure 8. output turn off time v in = ch1, v out = ch2 figure 9. flag going up delay v out = ch3, flag = ch2 figure 10. alert delay v out = ch1, flag = ch3 figure 11. initial overvoltage delay v in = ch1, v out = ch2, flag = ch3 figure 12. disable time en = ch1, v out = ch2, flag = ch3
ncp348, ncp348ae http://onsemi.com 7 typical operating characteristics figure 13. inrush current with c out = 100 f, i charge = 1 a, output wall adaptor inductance 1 h figure 14. output short circuit figure 15. output short circuit (zoom fig. 14)
ncp348, ncp348ae http://onsemi.com 8 voltage detection in out conditions v in > ovlo 0 < v in < uvlo and/or /en = 1 voltage detection in out conditions /en = 0 & uvlo < v in < ovlo figure 16. simplified diagram figure 17. simplified diagram operation the ncp348 provides overvoltage protection for positive voltage, up to 28 v. a low r ds(on) nmos fet protects the systems (i.e.: charger) connected on the vout pin, against positive overvoltage. at powerup, with en pin = low, the output is rising up 50 ms after the input overtaking undervoltage uvlo (figure 3). the ncp348 provides a flag output, which alerts the system that a fault has occurred. a 50 ms additional delay, regarding available output (figure 3) is added between output signal rising up and to flag signal rising up. flag pin is an open drain output.
ncp348, ncp348ae http://onsemi.com 9 timer check check v in flag = low timer count timer check v in < uvlo or v in > ovlo check en check en v out = v in flag = high check v in v out = open flag = high check v in figure 18. state machine ovlo > v in > uvlo t < 50 ms t = 50 ms reset timer v out = 0 flag = low reset timer v in < uvlo or v in > ovlo v out = 0 flag = low timer count uvlo < v in < ovlo en = 0 en = 1 v in < uvlo or v in > ovlo uvlo < v in < ovlo en = 0 en = 1 t = 50 ms v out = open v in < uvlo or v in > ovlo t < 50 ms uvlo < v in < ovlo v out = v in
ncp348, ncp348ae http://onsemi.com 10 undervoltage lockout (uvlo) to ensure proper operation under any conditions, the device has a built ? in undervoltage lockout (uvlo) circuit. during v in positive going slope, the output remains disconnected from input until v in voltage is below 3.25 v (ncp348mtt version), plus hysteresis, nominal. the flag output is tied to low as long as v in does not reach uvlo threshold. this circuit has a 50 mv hysteresis to provide noise immunity to transient condition. additional uvlo thresholds ranging from uvlo can be manufactured. (see selection guide on page 12) contact your on semiconductor representative for availability. overvoltage lockout (ovlo) to protect connected systems on v out pin from overvoltage, the device has a built ? in overvoltage lockout (ovlo) circuit. during overvoltage condition, the output remains disabled as long as the input voltage exceeds 6.4 v typical (ncp348mtt version). additional ovlo thresholds ranging from ovlo can be manufactured. (see selection guide on page 12) contact your on semiconductor representative for availability. flag output is tied to low until v in is higher than ovlo. this circuit has a 100 mv hysteresis to provide noise immunity to transient conditions . flag output the ncp348 provides a flag output, which alerts external systems that a fault has occurred. this pin is tied to low as soon the ovlo threshold is exceeded or when the v in level is below the uvlo threshold. when v in level recovers normal condition, flag is held high, keeping in mind that an additional 50 ms delay has been added between available output and flag = high. the pin is an open drain output, thus a pull up resistor (typically 1 m , minimum 10 k ) must be added to v bat . minimum v bat supply must be 2.5 v. the flag level will always reflects v in status, even if the device is turned off (en = 1). en input to enable normal operation, the en pin shall be forced to low or connected to ground. a high level on the pin, disconnects out pin from in pin. en does not overdrive an ovlo or uvlo fault. internal nmos fet the ncp348 includes an internal low r ds(on) nmos fet to protect the systems, connected on out pin, from positive overvoltage. regarding electrical characteristics, the r ds(on) , during normal operation, will create low losses on v out pin. as example: r load = 8.0 , v in = 5.0 v typical r ds(on) = 65 m i out = 618 ma v out = 8 x 0.618 = 4.95 v nmos losses = r ds(on) x iout 2 = 0.065 x 0.618 2 = 25 mw esd tests the ncp348 input pin fully supports the iec61000 ? 4 ? 2. 1.0 f (minimum) must be connected between v in and gnd, close to the device. that means, in air condition, v in has a 15 kv esd protected input. in contact condition, v in has 8.0 kv esd protected input. please refer to figure 19 to see the iec 61000 ? 4 ? 2 electrostatic discharge waveform. figure 19. electrostatic discharge waveform pcb recommendations the ncp348 integrates a 2 amperes rated nmos fet, and the pcb rules must be respected to properly evacuate the heat out of the silicon. the pad1 is internally isolated from the active silicon and should preferably be connected to ground. the pad2 of the ncp348 package is connected to the internal nmos drain and can be used to increase the heat transfer if necessary from an applications standpoint. depending upon the power dissipated in the application, one can either use the pcb tracks connected to pins 4 and 5 to evacuate heat, or make profit of the pad2 area to add extra copper surface to reduce the junction temperature (see figure 20). of course, in any case, this pad shall be not connected to any other potential. figure 20 shows copper area according to r ja and allows the design of the heat transfer plane connected to pad2.
ncp348, ncp348ae http://onsemi.com 11 figure 20. 270 0 25 50 75 100 125 150 175 ja ( c/w) copper heat spreading area (mm 2 ) 250 230 210 190 175 150 1 oz c.f. 310 290 200 225 250 275 300 325350 2 oz c.f. 1 oz sim 2 oz sim 2 1 figure 21. demo board layout 1 f 25 v x5r 0603 c1 en in in in flag nc nc out out ncp348 gnd 2 5 4 1 10 6 7 8 9 3 en 100 k r3 1 2 3 100 k r2 output 100 nf 50 v x7r 0805 not necessary c2 1 2 r1 1 m j2 flag power flag_state 1 2 gnd f1 f2 f3 f4 figure 22. demo board schematic en_state input en_power flag murata grm188r61e105ka12d
ncp348, ncp348ae http://onsemi.com 12 ordering information device package shipping ? ncp348mttbg wdfn ? 10 (pb ? free) 3000 / t ape & reel NCP348MTTXG wdfn ? 10 (pb ? free) 10000 / tape & reel ncp348aemttbg wdfn ? 10 (pb ? free) 3000 / tape & reel ncp348aemttxg wdfn ? 10 (pb ? free) 10000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd801 1/d. selection guide the ncp348 can be available in several undervoltage and overvoltage thresholds versions. part number is designated as follows: a ncp348xxmttxg bc code contents a uvlo typical threshold a: ? = 3.25 v a: a = 3.25 v b ovlo typical threshold b: ? = 6.4 v b: e = 6.02 v c tape & reel type c: b = 3000 c: x = 10000
ncp348, ncp348ae http://onsemi.com 13 package dimensions wdfn10, 2.5x2, 0.5p case 516aa ? 01 issue c *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting t echniques reference manual, solderrm/d. soldering footprint* 1.13 2.50 0.50 0.05 0.73 10x dimensions: millimeters 0.58 0.95 pitch 0.30 10x notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30mm from terminal. 4. coplanarity applies to the exposed pad as well as the terminals. c a seating plane d b e 0.10 c a3 a a1 2x 2x 0.10 c dim a min nom millimeters 0.70 0.75 a1 0.00 --- a3 0.20 ref b 0.20 0.25 d 2.50 bsc d2 0.97 1.08 e 2.00 bsc 0.80 0.90 e2 e 0.50 bsc 0.375 bsc g pin one reference 0.08 c 0.10 c 10x a 0.10 c note 3 l e d2 e2 b b 5 6 10x 1 10 10x 0.05 c 8x 0.20 0.30 l g1 a 0.10 cb 0.05 c d3 g a 0.10 cb 0.05 c k d3 0.57 0.68 g1 0.35 bsc k 0.20 --- 0.80 0.05 0.30 1.18 1.00 0.40 0.78 --- max on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, in cluding without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different a pplications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical e xperts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc prod uct could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney f ees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was neglig ent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 ncp348/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc a sales representative

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